Welcome to Verilog-to-Routing’s documentation!

Form more information on the Verilog-to-Routing (VTR) project see VTR and VTR CAD Flow.

For documentation and tutorials on the FPGA architecture description langauge see: FPGA Architecture Description.

For more specific documentation about VPR see VPR.

Usage

• VTR
  • VTR CAD Flow
  • Get VTR
  • Install VTR
  • Running the VTR Flow
  • Benchmarks
  • Power Estimation
  • Tasks
  • run_vtr_flow
  • run_vtr_task
  • parse_vtr_flow
  • parse_vtr_task
  • Parse Configuration
  • Pass Requirements
• FPGA Architecture Description
  • Architecture Reference
  • Example Architecture Specification
• VPR
  • Command-line Options
  • Graphics
  • Timing Constraints
  • SDC Commands
  • File Formats
  • Debugging Aids
• Odin II
  • INSTALL
  • USAGE
  • DOCUMENTING ODIN II
  • TESTING ODIN II
  • USING MODELSIM TO TEST ODIN II
  • CONTACT
• ABC
• Tutorials
  • Design Flow Tutorials
  • Architecture Modeling
  • Running the Titan Benchmarks
  • Post-Implementation Timing Simulation
• Utilities
  • FPGA Assembly (FASM) Output Support

Development

• Developer Guide
  • Building VTR
  • Contribution Guidelines
  • Commit Procedures
  • Code Formatting
  • Running Tests
  • Debugging Failed Tests
  • Evaluating Quality of Result (QoR) Changes
  • Adding Tests
  • Debugging Aids
  • External Subtrees
  • Finding Bugs with Coverity
  • Release Procedures
  • New Developer Tutorial
  • VTR Support Resources
  • VTR License

Appendix

• Contact
  • Mailing Lists
  • Issue Tracker
• Glossary
• Publications & References

Indices and tables

• Index
• Search Page